Over the last few decades, the electronics industry has continually driven towards higher performance and functionality in smaller form factors. At the production level, these driving forces have translated into smaller circuit features, designs and manufacturing methods that support more efficient circuit routing, elimination of layers of packaging, and sophisticated engineered materials. Issues that have been exacerbated by these trends include thermal management and management of the thermo-mechanical stresses generated by close juxtaposition of dissimilar materials.
One example of how the design of printed circuit boards and semiconductor packaging has changed to facilitate improvements in density is how the layers of circuitry are interconnected. In order to optimize circuit routing for speed and performance, it is necessary to shift from a through hole vertical interconnection architecture to a direct layer-to-layer interconnection architecture. Ideally the conductive vias that interconnect layers of circuitry are commensurate in size with the circuit traces that they interconnect, provide rugged and reliable conduction, require very small connecting circuit features, and can be stacked and otherwise freely placed anywhere in the circuit board or package design.
It is cost prohibitive to plate solid metal vias to form such layer-to-layer interconnections and entrapment of plating solution is a significant issue. The prevalent solution is to plate the topography of the via hole to a reasonable thickness. This strategy creates mechanical stress points at the edge of the via and where the plating connects with the underlying pad. The dimple created in the center of the via is also a potential source of defects. One solution is to fill the via hole with a conductive compound, but prior art via fill materials do not form electrically robust interfaces with the copper pads.
In addition to miniaturization of electronic devices, there is an emerging trend to integrate devices or elements thereof directly into other objects. Realization of these types of devices will require truly 3-D architectures and manufacturing methods. Innovative interconnection strategies will be required for applications as diverse as interconnecting the I/Os of stacked semiconductor die, creating conformable or embedded antenna structures for wireless devices and creating collection grids on solar panels.
An additional major trend in the electronics industry is the reduction and elimination of environmental hazards and toxins, including volatile organic compounds and lead. The elimination of lead in particular has complicated the manufacture of electronic devices as this element has been used extensively in the past. High tin alloys have emerged as a replacement for tin-lead. But these high tin alloys have melting temperatures roughly 30° C. higher than the prior tin-lead alloys, resulting in commensurate increases in component assembly process temperatures. The higher process temperatures increase the thermo-mechanical stresses on the increasingly fine-featured electrical interconnects.
As semiconductor packaging and printed circuit board production converge, substantial engineering effort has been devoted to the creation of materials than can withstand the rigors of the new architectures and processing regimes. For instance, the microstructure of the copper foils used to produce the fine circuits is extensively controlled. Another example would be the composite laminates used to create circuit substrates which have undergone extensive product development to control flow characteristics, glass transition temperature, coefficient of thermal expansion, and high quality hole formation. Surface preparation chemistries and primer coatings have also been extensively characterized and optimized. Barrier metals and surface finishes are applied to strict tolerances and dopants are added to solder materials to improve the mechanical characteristics of solder joints and prevent undesirable microstructures such as tin whiskers from forming.
A promising new material type that may satisfy many of the industry requirements for interconnection challenges is liquid phase sintering (TLPS) materials, which were introduced as a reliable and versatile conductives that could be applied to support a variety of configurations. Primarily lead-based commercial alloys were blended with copper particles in a fluxing binder to create these compositions.
The compositions could be processed like conventional lead-tin solders and formed robust metallurgical junctions to solder wettable surfaces, but, unlike solder, the compositions essentially created a metal “thermoset” during processing. This “thermosetting” characteristic was advantageous because the paste materials could be used on or in the circuit boards, or in operations in which step soldering was typically required, and the processed composition would not re-melt at the original process temperature.
These early TLPS materials were designed as a simple “thermosetting solder” with a self-inerting flux. The requirements for these early TLPS materials were that they metallurgically react to form a highly electrically conductive interconnection, remain solid through subsequent thermal processing, self-inert, and present a reasonably solderable surface. The microstructure of the metal network formed and the surrounding organic matrix were optimized only to the extent that electrical conductivity or characteristics such as adhesion were improved. The size of the interconnections was relatively large and the processed TLPS materials were rarely subjected to subsequent thermal excursions in excess of 220° C.
The early TLPS materials benefited from the availability of lead as a constituent material. Lead based solders offer a low process temperature, excellent wetting of copper, reasonably good electrical and thermal conductivity, and ductile, predominantly lead, bridges between the copper-tin intermetallic sheathed copper particles in the cured composition. Elimination of lead as a viable constituent metal presented a significant challenge to realizing the potential of the technology.
Despite the above described measures and advances, there still remains a need for compositions and methods for making thereof that can provide an inexpensive, robust, low process temperature, and reliable electrical and thermal interconnection strategy at several critical junctions within electronic devices. The present application provides such compositions and devices.